The present disclosure relates to a semiconductor device, and more particularly, to a refresh controlling circuit.
In LPSDR or LPDDR, selection of a partial array self refresh (PASR) Map can be determined within a preset bank region. Accordingly, such a selection is possible by controlling only a bank active signal.
FIG. 1 exemplarily illustrates a conventional 4-bank PASR Map.
Referring to FIG. 1, a self refresh region is determined according to a mode register set (MRS). In the conventional art, the bank cannot be arbitrarily set and it is possible to select only a Full-Array, ½ Array, or ¼ Array. In other words, it is impossible to set only the Bank 1 as a self refresh region.
FIG. 2 illustrates a block diagram of a conventional self refresh controlling circuit including a bank active control unit, a MRS latch and a PASR decoder. FIG. 3 illustrates a circuit diagram of the bank active control unit of FIG. 2, FIG. 4 illustrates a circuit diagram of the MRS latch unit of FIG. 2, and FIG. 5 illustrates a circuit diagram of the PASR decoder of FIG. 2.
When the MRS is set as shown in the table of FIG. 1, values of PAR1 and PAR23 are determined. When Full-Array or ½ Array is selected, the PAR1 is activated to a logic high level. Only when Full-Array is selected, the PAR23 is activated to a logic high level. Bank active control units are provided in a same number as the number of banks.
An output signal BA<0:3> of the bank active control unit is activated to a logic high level when an input signal PAR_EN is at a logic high level and a self refresh active pulse signal SREFREQP is toggled to a logic high level.
Since Bank 0 can be always self-refreshed according to the table of FIG. 1, the PAR_EN of the bank active control unit of Bank 0 is always fixed to a logic high level. The PAR_EN of the bank active control unit of Bank 1 is connected with PAR1, and the PAR_ENs of the bank active control units of Banks 2 and 3 are connected with PAR23.
If ¼ Array is selected through the MRS, PAR1 and PAR23 are all at a logic low level. Accordingly, if the self refresh active pulse signal SREFREQP is toggled, only the BA<0> is activated to a logic high level.
If ½ Array is selected, only PAR1 becomes a logic high level and accordingly BA<0> and BA<1> are activated to a logic high level. That is, only the bank 0 and bank 1 are enabled.
If Full Array is selected, PAR1 and PAR23 are all at a logic high level. Accordingly, each of BA<0:3> becomes a logic high level, so that all banks are enabled.
Thus, the conventional self refresh controlling circuit cannot be set to refresh only a specific region of each bank or each segment within each bank.